JPH0523055B2 - - Google Patents

Info

Publication number
JPH0523055B2
JPH0523055B2 JP58179551A JP17955183A JPH0523055B2 JP H0523055 B2 JPH0523055 B2 JP H0523055B2 JP 58179551 A JP58179551 A JP 58179551A JP 17955183 A JP17955183 A JP 17955183A JP H0523055 B2 JPH0523055 B2 JP H0523055B2
Authority
JP
Japan
Prior art keywords
source
heat treatment
film
drain diffusion
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58179551A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6072272A (ja
Inventor
Yoshitaka Tsunashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP58179551A priority Critical patent/JPS6072272A/ja
Priority to US06/606,403 priority patent/US4575920A/en
Priority to EP84306268A priority patent/EP0139467B1/en
Priority to DE8484306268T priority patent/DE3468149D1/de
Publication of JPS6072272A publication Critical patent/JPS6072272A/ja
Publication of JPH0523055B2 publication Critical patent/JPH0523055B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/605—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having significant overlap between the lightly-doped extensions and the gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H10D64/259—Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP58179551A 1983-09-28 1983-09-28 半導体装置の製造方法 Granted JPS6072272A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP58179551A JPS6072272A (ja) 1983-09-28 1983-09-28 半導体装置の製造方法
US06/606,403 US4575920A (en) 1983-09-28 1984-05-02 Method of manufacturing an insulated-gate field-effect transistor
EP84306268A EP0139467B1 (en) 1983-09-28 1984-09-13 Method of manufacturing an insulated-gate field-effect transistor
DE8484306268T DE3468149D1 (en) 1983-09-28 1984-09-13 Method of manufacturing an insulated-gate field-effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58179551A JPS6072272A (ja) 1983-09-28 1983-09-28 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS6072272A JPS6072272A (ja) 1985-04-24
JPH0523055B2 true JPH0523055B2 (en]) 1993-03-31

Family

ID=16067718

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58179551A Granted JPS6072272A (ja) 1983-09-28 1983-09-28 半導体装置の製造方法

Country Status (4)

Country Link
US (1) US4575920A (en])
EP (1) EP0139467B1 (en])
JP (1) JPS6072272A (en])
DE (1) DE3468149D1 (en])

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5276346A (en) * 1983-12-26 1994-01-04 Hitachi, Ltd. Semiconductor integrated circuit device having protective/output elements and internal circuits
US5610089A (en) * 1983-12-26 1997-03-11 Hitachi, Ltd. Method of fabrication of semiconductor integrated circuit device
JPH0695563B2 (ja) * 1985-02-01 1994-11-24 株式会社日立製作所 半導体装置
US4641417A (en) * 1984-06-25 1987-02-10 Texas Instruments Incorporated Process for making molybdenum gate and titanium silicide contacted MOS transistors in VLSI semiconductor devices
JPH0612822B2 (ja) * 1984-07-27 1994-02-16 株式会社日立製作所 半導体装置
DE3530065C2 (de) * 1984-08-22 1999-11-18 Mitsubishi Electric Corp Verfahren zur Herstellung eines Halbleiters
US4653173A (en) * 1985-03-04 1987-03-31 Signetics Corporation Method of manufacturing an insulated gate field effect device
US4621413A (en) * 1985-06-03 1986-11-11 Motorola, Inc. Fabricating a semiconductor device with reduced gate leakage
US4703551A (en) * 1986-01-24 1987-11-03 Ncr Corporation Process for forming LDD MOS/CMOS structures
US4709467A (en) * 1986-03-13 1987-12-01 Advanced Micro Devices, Inc. Non-selective implantation process for forming contact regions in integrated circuits
EP0242540A1 (en) * 1986-04-21 1987-10-28 International Business Machines Corporation Method and structure for reducing resistance in integrated circuits
JPH0620140B2 (ja) * 1986-06-11 1994-03-16 株式会社日立製作所 薄膜トランジスタ
US5094980A (en) * 1986-06-27 1992-03-10 Digital Equipment Corporation Method for providing a metal-semiconductor contact
US5028554A (en) * 1986-07-03 1991-07-02 Oki Electric Industry Co., Ltd. Process of fabricating an MIS FET
US4791074A (en) * 1986-08-29 1988-12-13 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor apparatus
US4801555A (en) * 1987-01-14 1989-01-31 Motorola, Inc. Double-implant process for forming graded source/drain regions
US4774204A (en) * 1987-06-02 1988-09-27 Texas Instruments Incorporated Method for forming self-aligned emitters and bases and source/drains in an integrated circuit
US5016215A (en) * 1987-09-30 1991-05-14 Texas Instruments Incorporated High speed EPROM with reverse polarity voltages applied to source and drain regions during reading and writing
FR2624304B1 (fr) * 1987-12-04 1990-05-04 Philips Nv Procede pour etablir une structure d'interconnexion electrique sur un dispositif semiconducteur au silicium
US5212400A (en) * 1988-02-18 1993-05-18 International Business Machines Corporation Method of depositing tungsten on silicon in a non-self-limiting CVD process and semiconductor device manufactured thereby
CA1308496C (en) * 1988-02-18 1992-10-06 Rajiv V. Joshi Deposition of tungsten on silicon in a non-self-limiting cvd process
US5086008A (en) * 1988-02-29 1992-02-04 Sgs-Thomson Microelectronics S.R.L. Process for obtaining high-voltage N channel transistors particularly for EEPROM memories with CMOS technology
US4971929A (en) * 1988-06-30 1990-11-20 Microwave Modules & Devices, Inc. Method of making RF transistor employing dual metallization with self-aligned first metal
KR930002673B1 (ko) * 1990-07-05 1993-04-07 삼성전자 주식회사 고융점금속 성장방법
US5403760A (en) * 1990-10-16 1995-04-04 Texas Instruments Incorporated Method of making a HgCdTe thin film transistor
JPH04177770A (ja) * 1990-11-09 1992-06-24 Nec Corp 可変容量ダイオードおよびその製造方法
US5208168A (en) * 1990-11-26 1993-05-04 Motorola, Inc. Semiconductor device having punch-through protected buried contacts and method for making the same
US5086017A (en) * 1991-03-21 1992-02-04 Industrial Technology Research Institute Self aligned silicide process for gate/runner without extra masking
US5108954A (en) * 1991-09-23 1992-04-28 Micron Technology, Inc. Method of reducing contact resistance at silicide/active area interfaces and semiconductor devices produced according to the method
EP0686307A1 (en) * 1993-12-17 1995-12-13 National Semiconductor Corporation Refractory metal contact for a power device
KR100203131B1 (ko) * 1996-06-24 1999-06-15 김영환 반도체 소자의 초저접합 형성방법
US5877050A (en) * 1996-09-03 1999-03-02 Advanced Micro Devices, Inc. Method of making N-channel and P-channel devices using two tube anneals and two rapid thermal anneals
US6455385B1 (en) * 1998-01-07 2002-09-24 Advanced Micro Devices, Inc. Semiconductor fabrication with multiple low dose implant
US6569766B1 (en) * 1999-04-28 2003-05-27 Nec Electronics Corporation Method for forming a silicide of metal with a high melting point in a semiconductor device
JP3295931B2 (ja) * 1999-04-28 2002-06-24 日本電気株式会社 半導体装置の製造方法
CN102403256B (zh) * 2010-09-08 2014-02-26 上海华虹宏力半导体制造有限公司 赝埋层及制造方法、深孔接触及三极管

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1269359A (en) * 1968-08-22 1972-04-06 Atomic Energy Authority Uk Improvements in or relating to semiconductors and methods of doping semiconductors
US4005450A (en) * 1970-05-13 1977-01-25 Hitachi, Ltd. Insulated gate field effect transistor having drain region containing low impurity concentration layer
JPS5946107B2 (ja) * 1975-06-04 1984-11-10 株式会社日立製作所 Ｍｉｓ型半導体装置の製造法
JPS52135685A (en) * 1976-05-10 1977-11-12 Nec Corp Semiconductor device
US4384301A (en) * 1979-11-07 1983-05-17 Texas Instruments Incorporated High performance submicron metal-oxide-semiconductor field effect transistor device structure
JPS5818965A (ja) * 1981-07-28 1983-02-03 Toshiba Corp 半導体装置の製造方法
US4442589A (en) * 1981-03-05 1984-04-17 International Business Machines Corporation Method for manufacturing field effect transistors
JPS584924A (ja) * 1981-07-01 1983-01-12 Hitachi Ltd 半導体装置の電極形成方法
US4485550A (en) * 1982-07-23 1984-12-04 At&T Bell Laboratories Fabrication of schottky-barrier MOS FETs
US4498224A (en) * 1982-12-23 1985-02-12 Tokyo Shibaura Denki Kabushiki Kaisha Method of manufacturing a MOSFET using accelerated ions to form an amorphous region

Also Published As

Publication number Publication date
EP0139467B1 (en) 1987-12-16
US4575920A (en) 1986-03-18
JPS6072272A (ja) 1985-04-24
DE3468149D1 (en) 1988-01-28
EP0139467A1 (en) 1985-05-02

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